Earlier  
Posted Nick Remark
#openstack-cyborg - 2019-10-17
03:07:43 Sundar " Due to various constraints, we are unable to record Project Updates this Summit. ...
03:07:59 Sundar We suggest that as an alternative, you record your main updates in an etherpad and use that as a resource to share afterwards. ...
03:08:09 xinranwang Hi, all. Sorry for being late.
03:08:16 Sundar After the event, we’ll send out an email requesting slides and an etherpad link for each project. ...
03:08:36 shaohe_feng hi all
03:08:39 shaohe_feng sorry for late
03:08:43 Sundar Those materials will be placed on the Summit Schedule and we will notify the community once they are live. If you would like to record a version of your presentation and send us a link, we can also add that to the Schedule. "
03:08:46 chenke hi xinran ,shaohe.
03:08:52 Sundar That's the message
03:09:23 Yumeng Alright Thanks! make sense.
03:09:58 Sundar Please add your suggested topics to the PTG etherpad, linked above
03:10:24 Sundar Also, it would be good to have dinner as a team, as we have done before.
03:10:44 Sundar Does Thursday night (Nov 7) work for all of you?
03:11:46 chenke It's ok for me.
03:11:54 Yumeng +1
03:11:58 s_shogo +1
03:12:57 Sundar Cool. Let's go with that. If you want to bring anybody else, please go ahead.
03:13:47 chenke Cool.
03:13:52 Sundar I will let you all choose the restaurant! Please make sure it has vegetarian food. :)
03:15:50 Sundar #topic Doc patches
03:16:16 Sundar https://review.opendev.org/#/q/status:open+project:openstack/cyborg+branch:stable/train
03:16:29 Sundar Thanks to Xinran for backporting the doc patches to stable/train
03:16:50 Sundar These were in cyborg master but the release team cut the stable branch after RC1
03:17:59 Sundar Release team has said we can backport doc patches any time, and they will take effect wothout version number changes
03:18:03 Sundar *without
03:18:27 Sundar So, Yumeng and all, please review it.
03:18:49 xinranwang can we get bug fix patch in now, as the doc patch ;)
03:19:09 Yumeng ok, will do.
03:19:24 chenke Done.
03:19:48 Sundar Nope :( There was lots of resistance to backporting other patches. We can potentially do a point-release early in U if we really want, IMO, all that is beside the point till we get nova integ.
03:20:18 Sundar Once we get nova integ done, we have the option of doing an early point release instead of waiting for April/May
03:20:52 Sundar Basically, non-doc patches require version change.
03:21:09 xinranwang ok, got it.
03:21:43 xinranwang now the doc patch review has high priority.
03:22:01 Sundar Yes.
03:22:15 xinranwang when is the ddl for doc patches?
03:23:02 Sundar No deadline. Train is more or less done. So, we can backport any time
03:24:36 Sundar BTW, Cyborg got some free press in OpenStack press releases: https://www.zdnet.com/article/the-openstack-train-keeps-chugging-on/, https://www.theregister.co.uk/2019/10/15/openstack_train/
03:24:44 Sundar Kudos to all of you :)
03:25:30 Sundar In other news, Nova-Cyborg interaction spec (https://review.opendev.org/#/c/684151/) got +2 from Nova PTL. Need to follow up more.
03:26:11 xinranwang good news!
03:26:17 chenke Great
03:26:29 chenke will follow up.
03:27:52 Sundar The press articles sound a bit weak because they mentioned only the Nova spec merge. We haven't really claimed that Cyborg supports VM creation etc. in this release. The next release is going to dleiver the goods, and we should be able to make stringer statements.
03:28:03 Sundar *stronger
03:28:20 chenke Ye.
03:28:44 Sundar #topic AoB
03:28:50 chenke Cyborg is a popular project for openstack.
03:29:00 Sundar Yes
03:29:03 Sundar Anything else for today?
03:29:25 chenke I want to confirm that the version has been sent out. Does it make sense to change the documentation?
03:30:02 Sundar Are you asking if it is ok to change the docs after Train has shipped?
03:30:04 chenke If users take the version, they won't get the latest documents
03:30:33 Sundar Hmm, if they clone stable/train in the future, after we merge the doc patches, they will get them all.
03:30:33 chenke Has the train been sent out?
03:31:09 chenke Yes. If they clone the stable/train , they will get them.
03:31:15 Sundar More or less: https://review.opendev.org/#/c/687991/ has bene merged
03:31:53 Sundar I think they have some backend work. It should be done by this week, I think
03:32:31 shaohe_feng Will this release add more ACC support?
03:32:49 Sundar Do you mean if we get more drivers in U?
03:32:49 shaohe_feng another questions.
03:32:54 shaohe_feng yes.
03:33:02 shaohe_feng more drivers?
03:33:10 shaohe_feng any plane for it?
03:34:16 shaohe_feng Do we support apply FPGA pf to a VM?
03:34:36 Sundar We could. We need to talk about it. Right now, we got some drivers for GPU and Ascend. However, the maintainers are not regularly participating in Cyborg activities. That makes me concerned about maintenance. Also, we don;t have 3rd party CI for any driver yet. We are planning that for FPGAs, but what about other drivers?
03:35:01 Sundar I was replying about drivers, not PF
03:35:27 shaohe_feng so the questions is that.
03:35:43 shaohe_feng If a end user apply a FPGA
03:35:43 Sundar As a team, we may have to decide on a higher bar for drivers. That is something we can discuss here on at the PTG.
03:35:45 Sundar *or
03:35:56 shaohe_feng I will not attend PTG.
03:36:29 Sundar Ah yes, too bad. You can give your ideas here or in the PTG etherpad.
03:36:30 shaohe_feng if he found there's bug on his bitstream?
03:36:50 shaohe_feng what should he do?
03:37:06 shaohe_feng delete the VM, rebuild a new VM with a FPGA?
03:37:14 Sundar Passing a FPGA PF to a VM is potential security hole, because we don;t know what bitstreams get programmed
03:37:14 s_shogo Wow, it's so good > CI for FPGA driver's.
03:37:22 shaohe_feng or just re-program it?
03:38:21 Sundar We have a usage model called Runtime Programming, which we don't support today. It involves VM issuing requests for new bitstreams, Cyborg or something receives that request and does the reprogramming. We don;t see many customers asking for that
03:38:42 shaohe_feng maybe, the end user after doing his AI, then he want to change the AI model, which means he maybe need a new bitstream for his AI net model.
03:38:48 shaohe_feng what should he do?
03:39:16 xinranwang I think we can provider a program interface for this kind of users.
03:39:25 xinranwang in vf use case.
03:39:44 Sundar He could get the VM to issue a request somehow to underlying infra. That is not there today. Today, he only needs to stop that VM and start a new one
03:40:13 Sundar xinranwang: User cannot reprogram a FPGA via VF.
03:40:59 shaohe_feng yes, but he take a great effort to setup his AI env, such as install the openvino and the dependency, set connection with the camera maybe.
03:41:07 xinranwang if boot with bit-stream failed, vm should become failed. if user boot a vm successfully, and want reprogram the FPGA, what will we do.
03:41:27 shaohe_feng so should should delete vm, rebuild one, and take effort to setup the env again?
03:42:58 shaohe_feng Seams now, the user just can use FPGA as fix function PCI devices once he create the VM
03:43:29 Sundar If there is a strong customer demand for that, have that customer(s) call Intel. This use case will require changes in the product level, software stack and in Cyborg. It will also require discussion among ourselves in Cyborg community.
03:44:21 shaohe_feng I did not seen the flexible advantage of FPGA.
03:44:44 xinranwang hat is a problem.
03:44:52 xinranwang * That
03:45:09 Sundar There are different usage models of FPGA. Many customers are adopting it with the current software stack.
03:45:21 Sundar Perhaps we can take this offline, rather than hold everybody up.
03:45:22 shaohe_feng the question is that, cyborg is not adopt in a product at present. So we miss so many customer demand for end user.
03:45:23 xinranwang IMHO, Cyborg should support reprogram right?
03:45:53 Sundar xinranwang: It should and it does today (at least will after Nova integ).
03:46:59 xinranwang Sundar: Yes, so I think it is doable for user who want update their bitstream.

Earlier   Later