Earlier  
Later
New Search
Posted Nick Remark
#openstack-cyborg - 2018-01-17
15:22:14 zhipeng zhuli could you take a look at jkilpatr's problem ?
15:22:54 Li_Liu Zhuli, yes, that's what I meant
15:24:00 Li_Liu the attributes table should be transparent to users
15:25:24 zhuli jkilpatr, tox can support both linters check and unit test according to your command, for instance 'tox -epep8' for linters and 'tox -epy27' for unittest
15:27:53 zhuli the openstack-tox-pep8 and openstack-tox-py27 gerrit jobs run against these two situation
15:28:47 jkilpatr ok there we go I'll wf it
15:29:04 jkilpatr unless crushil_ has objections?
15:31:06 zhuli jkilpatr, you can see the detail in these links
15:31:07 zhuli http://logs.openstack.org/96/527396/11/check/openstack-tox-pep8/185864a/job-output.txt.gz#_2018-01-13_18_12_47_975849
15:31:18 zhuli http://logs.openstack.org/96/527396/11/check/openstack-tox-py27/7cf69da/job-output.txt.gz#_2018-01-13_18_08_40_533805
15:34:37 zhipeng_ #info crushil_'s generic driver
15:34:41 zhipeng_ #link https://review.openstack.org/525057
15:34:45 zhipeng_ crushil_ any ETA on a full implementation ready for review and landing ?
15:34:48 zhuli liliu, ok, I'm ok with this, will help merge the patch if there is no other objections
15:35:10 Li_Liu Thanks a lot Zhuli
15:35:36 crushil_ zhipeng_, It's almost ready. Need to write accompanying unit tests
15:35:55 crushil_ You can start reviewing now
15:35:59 zhipeng_ sounds gr8t !
15:36:15 zhipeng_ #action land zhuli's pacth today
15:36:31 zhipeng_ #action start reviewing crushil_'s generic driver patch
15:37:03 zhipeng_ i think what we miss now is the conductor's report functionality to sync up resource info with Placement
15:37:14 zhipeng_ jkilpatr could you help on this ?
15:37:30 zhipeng_ on the basis of zhuli's patch
15:37:54 Vipparthy Also Zhipeng, Any feedback on Cyborg-Nova Integration Code
15:38:15 jkilpatr zhipeng_, this is on crushil_'s patch?
15:38:30 jkilpatr or zhuli's patch?
15:38:51 zhipeng_ zhuli's
15:39:17 jkilpatr I'll look at it
15:39:31 zhipeng_ something like adding a report.py from nova-compute to cyborg-conductor
15:39:42 zhipeng_ with the corresponding modifications
15:40:45 zhipeng_ #action jkilpatr to start working on the cyborg-conductor report function
15:41:13 zhipeng_ Vipparthy the above mentioned code is about the cyborg-nova integration
15:41:27 zhipeng_ Dutch dude are you still around ?
15:43:58 zhipeng_ $topic Xilinx SDAccel introduction
15:44:07 zhipeng_ #topic Xilinx SDAccel introduction
15:45:29 zhipeng #topic Xilinx SDAccel introduction
15:45:50 zhipeng So I'm glad to have Dutch from Xilinx to join our dev team
15:45:58 zhipeng Dutch the floor is yours sir
15:46:30 zhuli dutch welcome
15:47:20 Dutch Thanks! Hey everyone, I work with the Xilinx SDAccel team on our cloud program. I can help provide any resources or support from Xilinx. Also can help with SDAccel framework in general
15:48:10 Dutch We are still coming up to speed on the Cyborg project but the project looks great and we are happy to get involved
15:49:54 zhipeng Dutch could you provide some info on SDAccel ?
15:50:37 Dutch Sure, SDAccel is basically the framework for PCIe attached Xilinx FPGAs. Currently we use two PFs. PF0 is user space for DMA and PF1 is management for ioctls
15:52:02 Dutch Are people familiar with the driver at all?
15:52:17 zhipeng I think you could give a quick overview :P
15:52:52 Dutch Haha, I can't say I have done it over IRC before, this is usually consumed in slides with lots of images
15:53:39 Dutch Also, caution, I am not on the drivers team, so there are times when I don't know all the details
15:53:42 zhipeng haha i know
15:53:55 zhipeng maybe you could drop a link here ?
15:54:01 zhipeng for a good overview slide ?
15:54:29 Dutch Sure #link https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/index.html
15:54:37 zhuli thanks, that's very helpful
15:55:20 Dutch These are most of the user guides in one place instead of dealing with the PDFs, contents are the same
15:55:21 zhipeng gr8t thx!
15:55:40 zhipeng are there any support yet in the OpenStack for SDAccel ?
15:55:46 zhipeng for example nova driver ?
15:56:41 Dutch There is also a helpful platform guide UG1164, this is still a PDF
15:56:47 Dutch #link https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1164-sdaccel-platform-development.pdf
15:57:11 NokMikeR are there any xilinx parts with an open bitstream? (and tools to program them)?
15:57:33 Dutch Still no nova support, our openstack cluster is using pass-through, which as you can image is a serious limitation
15:59:08 Dutch The drivers could be open, but bitstream generation is IP so unlikely we will ever see that open
16:00:00 Dutch NokMikeR, what in particular do you want open?
16:00:40 NokMikeR any way to program the device via e.g an arm cpu so the synthesis and routing is done on the board - that way the entry level for the programmer is lower.
16:03:13 Dutch For drivers and runtime, absolutely. For synthesis and P&R, I am less sure.
16:04:01 Dutch I am also not sure what "done on the board" means
16:04:59 NokMikeR pcie board with fpga + additional cpu to generate the bitstream. you send that vhdl/verilog, "other code" and it all magically works :)
16:05:34 NokMikeR self contained basically. no reliance on vivado etc.
16:06:10 NokMikeR anyhow we are offtopic here, so Howard please carry on :)
16:06:26 zhipeng no this is actually an interesting topic :P
16:06:27 Dutch It is nice to think about but yeah, I would say that is a ways off
16:07:25 zhipeng NokMikeR I know there are open source bitstream FPGA cards, but not sure if it is production level
16:07:46 Dutch It might be possible to run Vivado on the add-in-card but as far as Vivado being open that seems very unlikely
16:08:03 Dutch I would push the currently open project to do something like this
16:08:25 zhipeng Dutch so coming back to SDAccel, the software defined here refering to ?
16:09:25 Dutch SDAccell was initially built to support OpenCL memory model, and there is also support for OpenCL kernel code
16:09:49 Dutch but it has advanced some to support iteration of HLS C and RTL IP
16:10:21 zhipeng got it
16:10:38 Dutch It was designed to be flexible so that it would support future models, MPI for example
16:11:10 zhipeng folks thx very much for the gr8t discussion today, i'm afraid I have to close the meeting now
16:11:45 zhipeng please go help reviewing the patch or drafting one, we have two weeks left before Queens code freeze
16:12:05 zhipeng so let's squeeze in as many stuff as we could :)
16:12:33 NokMikeR was the devstack bug report about the permissions for cyborg solved?
16:13:14 zhipeng yes NokMikeR
16:13:22 NokMikeR Great :)
16:14:09 zhipeng okey meeting adjourned
16:14:13 zhipeng #endmeeting
16:14:15 openstack Meeting ended Wed Jan 17 16:14:13 2018 UTC. Information about MeetBot at http://wiki.debian.org/MeetBot . (v 0.1.4)
16:14:16 openstack Minutes: http://eavesdrop.openstack.org/meetings/openstack_cyborg/2018/openstack_cyborg.2018-01-17-15.03.html
16:14:17 openstack Minutes (text): http://eavesdrop.openstack.org/meetings/openstack_cyborg/2018/openstack_cyborg.2018-01-17-15.03.txt
16:14:18 openstack Log: http://eavesdrop.openstack.org/meetings/openstack_cyborg/2018/openstack_cyborg.2018-01-17-15.03.log.html
16:14:49 Vipparthy Thank you folks
16:14:56 NokMikeR Thanks all, bye
16:15:12 Dutch Thanks!
17:51:07 guhcampos Hi folks, a quick question: I may need to implement our driver for cyborg. Is there a way to write it as a plugin? Like a separate python package that can be installed alongside cyborg? Or do I have to add it to cyborg's tree alongside the generic driver?
17:54:46 crushil_ guhcampos, Add it to Cyborg's tree alongside the generic driver
17:55:28 guhcampos crushil_, thanks. I needed this confirmation to pressure management to sign the contributor agreement
#openstack-cyborg - 2018-01-24
14:55:03 Vipparthy GM and GE folks
14:59:43 zhipeng yo
14:59:55 zhipeng Vipparthy good day :)
15:00:05 zhipeng #startmeeting openstack-cyborg

Earlier   Later