| Posted | Nick | Remark | |
|---|---|---|---|
| #openstack-cyborg - 2019-10-10 | |||
| 03:11:15 | chenke | https://github.com/openstack/cyborg/blob/master/cyborg/image/glance.py#L116 | |
| 03:11:28 | chenke | Sundar pls see this if condition | |
| 03:11:54 | Sundar | Yes. So, the api_servers config seems necessary, right? | |
| 03:11:59 | chenke | no | |
| 03:12:14 | chenke | The api_servers hide the else condition. | |
| 03:13:06 | chenke | now when I delete this api_servers, the else condition raise error because "/opt/stack/cyborg/cyborg/common/utils.py", line 208, in get_endpoint" | |
| 03:13:36 | chenke | What I want to say is that this problem was hidden before. | |
| 03:14:32 | Sundar | Got it. So, the api_servers is mor elike a hack or workaround to hide the error in the 'else' clause | |
| 03:14:49 | chenke | Right. | |
| 03:15:36 | chenke | After our meeting, I will find why the get_endpoint raise error. | |
| 03:15:37 | Sundar | Then the questions are: A. Do we have time to find the issue in the get_endpoint()? B. Is it worth fixing -- may be we should go straight to openstacksdk in U? | |
| 03:16:03 | chenke | maybe we could use openstacksdk. | |
| 03:16:33 | chenke | need to have a try. I am not sure now. But eric suggest glance to use openstacksdk before. | |
| 03:17:22 | Sundar | Yes, I believe we tried that approach and gave up because of a bug there. The opestacksdk patch which was suggested as a fix has since been abandoned. | |
| 03:18:06 | Sundar | Anyway, I agree this is a U-release conversation. Perhaps we should get started soon so that we can shoot for a resolution in November, early in the U cycle | |
| 03:18:55 | chenke | agree. | |
| 03:20:34 | Sundar | Cool, thanks Chenke | |
| 03:21:09 | Sundar | All, please review the documentation patches. We need to close them for the next RC. | |
| 03:21:56 | Sundar | Also, like I said, please review: https://review.opendev.org/684456 | |
| 03:22:15 | Sundar | #topic PTG prep | |
| 03:23:06 | Sundar | I will create an etherpad and share with you. Please indicate who among you plan to attend. | |
| 03:23:13 | xinranwang | next RC is this week or 18 Oct | |
| 03:24:25 | Sundar | xinranwang: The final RC is due this week. But I haven't seen a RC patch proposed yet. | |
| 03:24:32 | Sundar | 18 Oct is the release itself | |
| 03:25:30 | xinranwang | Sundar: Ok, I will review it by this week. | |
| 03:25:35 | Sundar | Yumeng: we need to work together for the project update. | |
| 03:26:07 | Yumeng | sundar: yes, I was about to ask. | |
| 03:26:19 | Yumeng | do you have any plans about the structure? | |
| 03:26:20 | Sundar | Just curious, who among you plan to attend the PTG (after the Summit)? | |
| 03:27:06 | Sundar | Yumeng: kind of. Can you access Google slides? | |
| 03:27:29 | xinranwang | I will attend Summit and PTG, and I am preparing a demo at Intel booth during the Summit which show qat use case in cyborg and performance improvement. | |
| 03:27:45 | shaohe_feng | hi all. | |
| 03:27:51 | Sundar | Cool | |
| 03:27:51 | shaohe_feng | sorry for late | |
| 03:28:07 | shaohe_feng | something wrong with my pc. | |
| 03:28:21 | Sundar | shaohe_feng: welcome, np | |
| 03:28:53 | chenke | hi shaohe. | |
| 03:29:07 | shaohe_feng | morning chenke | |
| 03:29:21 | Yumeng | Sundar: google doc not always available. It will be appreciate if u can send me the file directly! | |
| 03:29:33 | Sundar | DO any of you have specific ideas for U release? Such as new drivers, or improvements to Cyborg? (Apart from nova integ, which IMO is most important.) | |
| 03:29:43 | s_shogo | I'll attend the Summit and PTG (all day). | |
| 03:29:46 | Sundar | Yumeng: got it, will do | |
| 03:29:51 | Yumeng | I will attend Summit and PTG too | |
| 03:30:11 | Sundar | Great, s_shogo and Yumeng | |
| 03:30:31 | Sundar | Hope we'll get to meet chenke and zhurong too ;) | |
| 03:30:58 | xinranwang | Sundar: from Intel side, there are HDDL and QAT driver. We can do it in U release. | |
| 03:31:01 | chenke | I will attend Summit and PTG too. | |
| 03:31:18 | Sundar | Great | |
| 03:31:25 | shaohe_feng | Yes, HDDL and QAT | |
| 03:31:30 | Sundar | #topic AoB | |
| 03:31:38 | Sundar | Anything else to bring up today? | |
| 03:31:49 | shaohe_feng | for FPGA, should we support alias for function_id? | |
| 03:32:03 | shaohe_feng | such as in DP: | |
| 03:32:12 | zhurong | Sundar hope to see you too | |
| 03:32:38 | Sundar | shaohe: Yes, that would be a good addition. After nova integ. | |
| 03:32:45 | xinranwang | Yes, as shaohe said. it remains many TODOs and improvement in Cyborg, we can discuss during PTG. | |
| 03:32:47 | Sundar | zhurong: Yes, I plan to be there | |
| 03:33:03 | Sundar | My first trip to China :) | |
| 03:33:29 | chenke | Sundar welcome to china. | |
| 03:33:33 | shaohe_feng | "accel:function_id": "123_456_789_333", this is not friendly to user. | |
| 03:33:52 | shaohe_feng | Sundar welcome to china | |
| 03:34:06 | Sundar | Thanks | |
| 03:34:14 | xinranwang | welcome to China :) | |
| 03:34:23 | shaohe_feng | maybe "accel:function_alias": "SmartNic_V1" | |
| 03:34:30 | shaohe_feng | or other describe it. | |
| 03:35:10 | Sundar | Yes, let's brainstorm on the function_id stuff. Perhaps I should create an etherpad for that. | |
| 03:35:18 | xinranwang | Sundar: can you create a etherpad that we can add the idea on it. | |
| 03:35:25 | Sundar | Sure | |
| 03:35:28 | shaohe_feng | yes. | |
| 03:35:37 | shaohe_feng | a etherpad is good. | |
| 03:35:45 | Sundar | Cool. Anything else, folks? | |
| 03:35:51 | shaohe_feng | another things, now the async job is in API. | |
| 03:35:54 | xinranwang | And we can discuss them during the meeting | |
| 03:36:19 | shaohe_feng | we have issue, should be support async job in conductor or agent | |
| 03:36:35 | shaohe_feng | pros and cons? | |
| 03:36:47 | Sundar | IMHO it should be in the conductor | |
| 03:37:31 | shaohe_feng | OK, we can discuss and improve it. also put in etherpad | |
| 03:37:39 | Sundar | ok | |
| 03:38:32 | Sundar | From the next meeting, we can start focusing more on the PTG. | |
| 03:38:44 | shaohe_feng | also another thing, a mini improve for factory. | |
| 03:38:52 | shaohe_feng | https://stackoverflow.com/questions/3464061/cast-base-class-to-derived-class-python-or-more-pythonic-way-of-extending-class | |
| 03:39:00 | shaohe_feng | ^ #info link | |
| 03:39:26 | Sundar | Details like this are probably better discussed as a patch proposal, rather than in etherpad, I think | |
| 03:39:46 | shaohe_feng | this is no in etherpad. | |
| 03:39:53 | shaohe_feng | just discuss it here | |
| 03:40:10 | shaohe_feng | mini performance improvement | |
| 03:40:21 | shaohe_feng | now when I found it is a FPGA ARQ, I create a FPGA ARQ | |
| 03:40:36 | shaohe_feng | that means I access a DB again. | |
| 03:41:17 | shaohe_feng | we can cast base ARQ to FPGA ARQ to avoid the DB access | |
| 03:41:46 | Sundar | shaohe_feng: Ok. Please feel free to propose a patch with your ideas. | |
| 03:42:13 | shaohe_feng | do you think is it worth to do it? | |
| 03:42:17 | shaohe_feng | ^ Sundar | |
| 03:42:57 | Sundar | shaohe_feng: Yes. Not terribly sure about the casting across parent and child classes, though. That can be tricky. | |
| 03:43:34 | Sundar | Trying to avoid an extra db access makes sense. | |
| 03:43:43 | shaohe_feng | just a mini performance improvement. and mini patch. | |
| 03:43:56 | shaohe_feng | you can see this example in the link | |
| 03:44:01 | shaohe_feng | https://stackoverflow.com/questions/3464061/cast-base-class-to-derived-class-python-or-more-pythonic-way-of-extending-class | |
| 03:44:13 | shaohe_feng | from math import pi | |
| 03:44:17 | shaohe_feng | print repr(c) | |
| 03:44:29 | shaohe_feng | only one line change: | |